As the speed of devices and chips in computer systems increase, a generic problem which arises is how to integrate them with relatively slower components of the system. One solution is to synchronize the various elements with a system clock. This requires the clock cycle to be no faster than the response time of the slowest such element. An obvious drawback of this approach is that the system is forced to operate at the speed of the slowest element, thereby wasting the potential of the faster elements.
A specific problem to which the present invention is directed involves the application of a microprocessor chip with a relatively slower peripheral device. The microprocessor starts a data transfer operating cycle to the peripheral by asserting its address strobe. The address strobe is essentially a request signal for sending or receiving data. After a delay (the response time of the peripheral) the peripheral acknowledges the address strobe by sending a handshake signal to the microprocessor. When the microprocessor sees the handshake signal it removes its address strobe. In response, the peripheral removes the handshake signal and a new cycle may commence. A problem can arise if the fast microprocessor starts a new operating cycle by asserting a new address strobe signal before the peripheral is able to remove its first handshake signal. The microprocessor may interpret this residual handshake signal as a new handshake and terminate the new bus cycle prematurely.